Crosstalk noise generated by parasitic inductances in System-on-Chip VLSI interconnects

Brajesh Kumar Kaushik^*, Sankar Sarkar, Rajendra P. Agarwal, and Ramesh C. Joshi

For System-on-Chip (SoC) using deep sub-micron technologies, semi-global and global interconnects are susceptible to crosstalk defects that may lead to mal-function and timing failures. Removal of crosstalk defects is becoming important to ensure error-free operation of an SoC. To efficiently evaluate crosstalk-defect coverage, it is necessary to understand the factors affecting this noise. In this paper, the results of study of noise induced by parasitic capacitance and inductance are observed. Crosstalk is effected by transition time of the signal; length of interconnect; distance between interconnects; size of driver and receiver; pattern of input; direction of flow of signal; and clock skew. This work is based on simulating interconnects with parameters obtained from 0.13mm process. The types of noise addressed are overshoot; undershoot and oscillatory noise. It is observed that presence of inductive effects can seriously hamper the functioning of the chip. In conclusion, the impact of the above observations on tests of inductance induced noise is summarized.

Keywords: VLSI, Crosstalk, RLC interconnect, simulation, over and under shoots.